Using this method, Synplify automatically creates the initial constraints file(s) for the design, finds the clocks and provides reports for the FPGA designer to utilize.įigure 2 Synplify timing report from autoconstrain showing three inferred clocks In addition to the initial FDC file creation, Synplify provides a method to “autoconstrain” any new design. The following provides an example of a newly created FPGA Design Constraint (FDC) file with some initial constraints and correct syntax for things like clocks, I/O, and clock groups.įigure 1 Initial FDC file created and automatically populated by Synplify They have an option to run a TCL utility within Synplify to create the initial FDC file for the design using the TCL: create_fdc_template command. When starting a new project, designers need to setup the environment and define the overall input for the design. Initial setup and identification of clocks There are many other set_options that can impact timing, including gated clock conversion, pipelining, and retiming. In addition to these constraints, the FPGA designer needs to set up their environment correctly – for example, setting the speed grade of the device in use with set_option-speed_grade. set_input_delay, set_output_delay, set_false_path, set_multicycle_path, and set_max_delay for defining all other constraints like I/O and any exceptions like false and multicycle paths.When adding IP, the designer needs to make sure that they include the associated constraint file which is usually supplied by the IP provider. syn_tpd, syn_tco, or syn_tsu for defining black box and IP block constraints.When defining the relationships, the designer needs to take care to make sure they are reasonable. create_clock, create_generated_clock, and set_clock_groups for defining all the clocks and relationships between clocks.Synplify helps designers do this by providing the following defined constraints and attributes: In general, FPGA designers need to define the clocks, IP & black boxes, and all other constraints like I/O. Define multi-cycle paths and false-paths.Identify and creating clock groupings and clock relationships.